Phase change technology is promising for next generation memories. It uses chalcogenide semiconductors for storing states. The chalcogenide semiconductors with phase change capability have a crystalline state and an amorphous state. In the crystalline state, the phase change materials have low resistivities, while in the amorphous state they have high resistivities. The resistivity ratios of the phase change materials in the amorphous and crystalline states are typically greater than 1000, and thus the resulting memory devices are unlikely to have errors for reading states. The chalcogenide materials are stable at certain temperature ranges in both crystalline and amorphous states and can be switched back and forth between the two states by electric pulses. One type of memory device that uses the principal of phase change in chalcogenide semiconductors is commonly referred to as phase change random access memory (PRAM).
Some phase change materials, such as Ge—Sb—Te alloys, may have three possible structures, amorphous structure, face-centered cubic (FCC) structure, and hexagonal close packed (HCP) structure. Amorphous phase has high resistivities, HCP phase has low resistivities, while FCC phase has resistivities between the amorphous phase and the HCP phase. Typically, an amorphous phase change material may be transformed to the FCC phase change material at about 150° C., while transforming an amorphous phase or a FCC phase to HCP phase requires about 360° C. or higher. Since the typical back end of processes require about 400° C., the resulting phase change materials in phase change memories, as fabricated, are likely to be at the HCP state.
Since HCP phase change materials have low resistivities, the reset current for the very first reset operation (initial reset operation) after the fabrication needs to be very high. In the subsequent operations, the phases of phase change materials are typically switched between the amorphous state and the FCC state. Therefore, the subsequent reset operations may be performed with smaller reset currents. However, the integrated circuits for providing reset currents need to support the initial reset operation by providing high reset currents, although the subsequent reset operations may only need smaller program currents. This is a serious issue for device operation. The reset current and also the difference between initial and subsequent reset must be reduced.
To make things worse, since there are process variations in forming the heaters for heating the phase change materials, different phase change memory cells may need different reset currents even if they are in a same chip. Clearly, the initial reset currents need to be high enough for resetting all phase change memory cells. This further demands even higher initial reset currents, and hence putting a higher requirement to the integrated circuits for providing the reset currents. In addition, power consumption is unnecessarily increased for non-initial reset operations due to higher-than-necessary reset currents. New phase change memories and methods for forming the same are thus needed.